The present invention relates to semiconductor devices, and more particularly, to a semiconductor device having a multilayer structure including a dual-layer silicide which has improved high-temperature stability. The multilayer structure can suitably be a polycide gate structure in a dynamic random access memory device (DRAM).
Refractory metal silicides have been widely utilized in applications demanding a gate or wiring material exhibiting low internal resistance. For example, titanium silicide, which is obtained by combining titanium (Ti), which is a refractory metal, with silicon (Si), exhibits excellent electrical conductivity and heat-resistance. Consequently, titanium silicide has found widespread commercial application in VLSI and ULSI processes for fabricating highly-integrated semiconductor memory devices and the like. Because of its remarkable heat-resistance, titanium silicide has particular utility in the fabrication of self-aligned silicide structures (salicides), e.g., such as is disclosed in IEDM 9-12, December, 1990, pp. 249-252.
With reference now to FIGS. 1A, 1B and 1C, successive steps of a conventional process for forming titanium silicide will now be described. With particular reference to FIG. 1A, a silicon dioxide (SiO2) layer 2 is grown to a thickness of approximately 1,000 xc3x85 on the upper surface of a monocrystalline silicon substrate 1 whose specific resistance is approximately 5-25 ohms/cm, e.g., by means of a thermal oxidation process carried out at approximately 920xc2x0 C. Next, a polycrystalline silicon layer 3 is deposited on the upper surface of the silicon dioxide layer 2 to a thickness of approximately 2,500 xc3x85, e.g., by means of a low pressure chemical vapor deposition (LPCVD) process carried out by way of thermally decomposing silane (SiH4) at a temperature of approximately 625xc2x0 C. in an atmosphere under a pressure of 250 mTorr. Then, phosphorus (P) impurities are ion-implanted into the polycrystalline silicon layer 3, e.g., a phosphorus dose of approximately 5xc3x971015 ions/cm2 is ion-implanted with an ion implantation energy of approximately 30 KeV. In order to prevent damage to the upper surface of the polycrystalline silicon layer 3 which may otherwise be caused by the ion implantation process, annealing is carried out in a furnace at approximately 900xc2x0 C. for about 30 minutes. Thereafter, titanium is deposited, by means of a sputtering process, on the upper surface of the polycrystalline silicon layer 3, to a thickness of approximately 400-600 xc3x85. The resultant structure is then rapidly annealed in a furnace at approximately 800xc2x0 C., in an argon (Ar) ambient atmosphere, for approximately 20 seconds. This rapid furnace annealing causes the polycrystalline silicon and the titanium of the polycrystalline layer 3 and the titanium layer 4, respectively, to chemically react with each other, thereby resulting in the formation of the titanium silicide layer 5 shown in FIG. 1B.
Above a respective silicon-forming temperature any refractory metal silicide film formed on underlying silicon begins to exhibit a high-temperature instability with metal atoms diffusing from the silicide film into the underlying silicon, so that silicon precipitates into the metal silicide film, the high-temperature instability temperature for any particular refractory metal silicide being known to be closely approximated by multiplying the absolute temperature of the melting point of the particular silicide by a factor of 0.6.
The melting point of titanium silicide is approximately 1540xc2x0 C. (1813xc2x0 K.), and its high-temperature instability theoretically begins at 814xc2x0 C., which is approximately 0.60xc3x97 its melting point, in terms of absolute temperature (i.e., xc2x0 K.). However, the melting point of titanium silicide varies slightly depending upon the particular processing parameters employed in its processing, but generally, its high-temperature instability begins at approximately 900xc2x0 C.
Consequently, when the resultant multilayer structure including the titanium silicide layer 5 is subjected to temperatures in excess of 900xc2x0 C. during a subsequent annealing step, the high-temperature instability of the titanium silicide causes problems such as grain growth, plastic deformation, and agglomeration, which induce discontinuites in the thin titanium silicide layer 5. These discontinuities are manifested as microscopic islands 6, as can be seen in FIG. 1C, thereby exposing portions of the upper surface of the silicon layer 3, which has the effect of significantly increasing the internal resistance of the titanium silicide layer 5.
Based on the above, it can be appreciated that there presently exists a need in the art for a multilayer structure including a silicide which eliminates the above-described shortcomings and disadvantages of the prior art. The present invention fulfills this need.
The present invention encompasses a semiconductor device which includes a silicon substrate, an oxide layer formed on the silicon substrate, a polysilicon layer formed on the oxide layer, a first metal silicide layer formed on the polysilicon layer, and a second metal silicide layer formed on the first metal silicide layer, and a method for fabricating the same. The first metal silicide layer is preferably comprised of a metal silicide, such as tungsten, molybdenum, or tantalum silicide, having a melting point which is higher than that of the second metal silicide layer. The second metal silicide layer is preferably comprised of titanium silicide. A multi-layer structure including a dual-layered silicide as described above avoids the prior art problems of agglomeration, grain growth, and plastic deformation of the silicide due to epitaxial growth of silicon, thus significantly decreasing its sheet resistance and improving its high-temperature stability.